Methods for Passivating Metallic Interconnects

ABSTRACT

One or more embodiments of the present invention relates to a method for passivating metallic interconnects, said method including: forming a metallic conductor embedded in at least one surrounding dielectric layer, said metallic conductor including a metal or alloy chosen from a group consisting of Cu, Ag, and alloys including one or more of these metals, said metallic conductor and said at least one surrounding dielectric layer having top surfaces; and forming a capping passivation film directly on the top surface of the metallic conductor, but not over the top surface of the at least one surrounding dielectric layer, wherein said capping passivation film including one or more materials selected from the group consisting of copper sulfide, silver sulfide, copper selenide, silver selenide, copper telluride, and silver telluride, wherein the copper sulfide refers to CuS X  or Cu 2 S X , the silver sulfide refers to AgS X  or Ag 2 S X , the copper selenide refers to CuSe X or Cu 2 Se X , and the copper telluride refers to CuTe X  or Cu 2 Te X , and wherein 0.7≦X≦1.3.

This is a Continuation of application Ser. No. 11/156,122, filed on Jun.17, 2005, now U.S. Pat. 7,709,958, which claims the benefit of U.S.Provisional Application No. 60/581,285, filed on Jun. 18, 2004, whichapplication is incorporated herein by reference.

Technical Field of the Invention

One or more embodiments of the present invention relates to the field ofVery Large Scale Integration (VLSI) and Ultra Large Scale Integration(ULSI) semiconductor devices, Thin Film Head (TFH) devices, MicroElectronic Machined Systems (MEMS), and high density electronic devicepackaging such as, for example and without limitation, Flip Chip, ChipScale Packaging (CSP), and Wafer Scale Packaging (WSP).

BACKGROUND OF THE INVENTION

In fabricating Damascene and Dual Damascene (DD) copper interconnects inaccordance with prior art techniques, copper is encased in one or morecopper diffusion barrier layers. Typically, the bilayer Ta/TaN_(X) isused as a barrier layer for sidewalls and at the bottom of lines, and arelatively high-k dielectric layer, typically silicon nitride (orsilicon carbide, or silicon carbide nitride, or silicon oxide carbidenitride), is used as a top capping barrier layer.

Sites of poor adhesion between copper and metallic barrier layers onsidewalls and/or at the bottom of openings may result inelectromigration (EM) and/or Stress Induced Voids (SIV). Copper EM andSIV are important reasons for poor reliability and low yields in copperinterconnects. Presently used sidewalls and bottom barrier layers, suchas Ta, TaN_(X), Ta/TaN_(X), Ru, TaSi_(X)N_(Y), WN_(X), Ti/TiN_(X),TiSi_(X)N_(Y), or WSi_(X)N_(Y), are problematic because: (a) theirrelatively high resistivity increases the resistance of interconnectlines and vias—this is particularly problematic at the bottom of vias;(b) they may have poor adhesion to copper and/or to the dielectricsurrounding the interconnect (inter layer dielectric or ILD), resultingin high EM and/or SIV; and (c) they are often discontinuously depositedby a PVD technique over sidewalls of high aspect ratio (HAR) Damasceneand Dual Damascene vias and trenches (particularly on hard to reachlower sidewalls of HAR openings, and on negative slope vicinities ofundercut crevices, nooks, and crannies)—which discontinuities provideeasy diffusion routes for copper into surrounding dielectric and/orcopper voids.

In light of the above, there is a need for methods and materials thatsolve one or more of the above-identified problems.

SUMMARY OF THE INVENTION

One or more embodiments of the present invention solve one or more ofthe above-identified problems. In particular, one or more embodiments ofthe present invention relate to methods for passivating metallicinterconnects, said method including: forming a metallic conductorembedded in at least one surrounding dielectric layer, said metallicconductor including a metal or alloy chosen from a group consisting ofCu, Ag, and alloys including one or more of these metals, said metallicconductor and said at least one surrounding dielectric layer having topsurfaces; and forming a capping passivation film directly on the topsurface of the metallic conductor, but not over the top surface of theat least one surrounding dielectric layer, wherein said cappingpassivation film including one or more materials selected from the groupconsisting of copper sulfide, silver sulfide, copper selenide, silverselenide, copper telluride, and silver telluride, wherein the coppersulfide refers to CuS_(X) or Cu₂S_(X), the silver sulfide refers toAgS_(X) or Ag₂S_(X), the copper selenide refers to CuSe_(X) orCu₂Se_(X), and the copper telluride refers to CuTe_(X) or Cu₂Te_(X), andwherein 0.7≦X≦1.3.

BRIEF DESCRIPTION OF THE FIGURES

FIGS. 1( a)-1(b) show a pictorial representation of a transverse (alongthe width) cross-section of an interconnect structure used to fabricate,for example and without limitation, a semiconductor device that includesa conductor structure fabricated in accordance with one or moreembodiments of the present invention;

FIGS. 2( a)-2(b) show a pictorial representation of a transverse (alongthe width) cross-section of an opening with its sidewalls covered with aconformal passivation and/or diffusion barrier film in accordance withone or more embodiments of the present invention;

FIGS. 3( a)-3(b) show a pictorial representation of a transverse (alongthe width) cross-section of an embedded (or filled) conductiveinterconnect with its sidewalls covered with a conformal passivationand/or diffusion barrier film, and its top surface covered with apassivation capping film in accordance with one or more embodiments ofthe present invention; and

FIGS. 4( a)-4(b) show a pictorial representation of a longitudinal(along the length) cross-section of an embedded (or filled) DualDamascene conductive interconnect where the interconnect is encased by apassivation and/or diffusion barrier film on its sidewalls and bottomsurfaces, and its top surface is covered with a passivation capping filmin accordance with one or more embodiments of the present invention.

DETAILED DESCRIPTION Top Capping

FIG. 1( a) shows a pictorial representation of a transverse (along thewidth) cross-section (not to scale for ease of understanding) ofstructure 100 used to fabricate, for example and without limitation, asemiconductor device that includes a conductor structure comprised ofconductive interconnect 18. Conductive interconnect 18 may comprise ametal or metal alloy such as, for example and without limitation, Cu,Ag, or alloys comprising one or more of these metals. Structure 100 maybe fabricated as follows. In accordance with any one of a number ofmethods that are well known to those of ordinary skill in the art,dielectric layer 11 may be deposited over substrate 10, which substrate10 may comprise one or more layers such as, for example and withoutlimitation, a lower metallization level and/or another dielectric layer.Next, in accordance with any one of a number of methods that are wellknown to those of ordinary skill in the art, an opening having sidewallsurfaces 15 and bottom surface 17 may be pattern-etched in dielectriclayer 11, and barrier layer 16 and one or more seed layers (not shown inFIG. 1) may be deposited over sidewalls 15 and bottom surface 17 of theopening. Barrier 16 may comprise, for example and without limitation, arefractory metal or an alloy comprising a refractory metal, such as Ta,TaN_(X), Ta/TaN_(X), Ru, TaSi_(X)N_(Y), WN_(X), Ti/TiN_(X),TiSi_(X)N_(Y), or WSi_(X)N_(Y). One or more seed layers (not shown) arethen deposited over the metallic barrier layer 16. Next, in accordancewith any one of a number of methods that are well known to those ofordinary skill in the art, for example and without limitation, usingelectrofilling methods, the opening may be filled with conductiveinterconnect 18. Next, in accordance with any one of a number of methodsthat are well known to those of ordinary skill in the art, for exampleand without limitation, using one or more planarization and/or removaltechniques, such as chemical mechanical polishing (CMP), polishing,electro-dissolution, electropolishing, or chemical etching, excessconductor in conductor 18 and excess conductor over dielectric 11 infield 14, as well as any seed and barrier layers overlying field 14, maybe removed to expose a top surface of conductor interconnect metal 18and a top surface of field 14. This step is sometimes referred to in theart as a removal or planarization step.

In accordance with one or more embodiments of the present invention,following the removal or planarization step, the exposed top surface ofconductor interconnect 18 is covered with passivation film 12. Inaccordance with one or more embodiments of the present invention, thestep of covering the exposed top surface of conductor interconnect 18with passivation film 12 comprises providing passivation film 12 overthe exposed top surface of conductive metal 18 by, for example andwithout limitation, an intermixing growth process or a depositionprocess.

The term “intermixing growth” process is defined herein as a process inwhich a film grows on a surface of a material, which film comprises oneor more constituents of the material and one or more constituents of areactant. One example, without limitation, of an intermixing growthprocess involves diffusion across a growing film of one or moreconstituents from the material to the surface of the growing film,and/or diffusion across the growing film of one or more constituentsfrom the reactant to the interface between the material and the growingfilm. For example and without limitation, silicon dioxide growth byoxidation of a silicon surface (such as described in a book entitled“VLSI Fabrication Principles” by S. K. Ghandhi, pp. 377-383, John Wiley& Sons, Inc. (1983)) is an intermixing growth process. The term“deposition” is defined herein as any process in which all of theconstituents of a film originate from reagents external to the surfaceof a material. Some examples, without limitation, of depositionprocesses are electrodeposition, electroless deposition, chemical bathdeposition (CBD), physical vapor deposition (PVD), chemical vapordeposition (CVD), and atomic layer deposition (ALD).

A. Intermixing Growth

In accordance with one or more embodiments of the present invention,passivation film 12 may be fabricated by reacting the exposed topsurface of conductor interconnect 18 with one or more reactants tofabricate one or more materials that adhere strongly to the exposedconductor 18 surface. In accordance with one or more such embodiments,it is believed that strong adhesion is provided because at least one ofsuch materials is chemically bonded to the material at the exposed topsurface of conductor interconnect 18. Advantageously, in accordance withone or more of such embodiments, it is believed that passivation film 12grows selectively, i.e., it grows only on exposed surface of conductorinterconnect 18, and not on dielectric 11 at the exposed surface offield 14.

In accordance with one or more embodiments of the present invention,conductor interconnect 18 comprises copper or a copper alloy, andpassivation film 12 comprises a copper sulfide such as CuS_(X) and/orCu₂S_(X) (where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds),and/or other materials comprising one or more of these compounds. Coppersulfide film 12 can be grown by an intermixing growth process, forexample and without limitation, by sulfidation of (or reacting) theexposed top surface of copper interconnect 18 with a sulfur-bearingreactant gas (or gas mixture) comprising sulfur atoms, molecules, orions such as, for example and without limitation, H₂S or vapors ofelemental sulfur (S_(n); where n is an integer). It is believed that inaccordance with such embodiments, copper sulfide film 12 is grown by anintermixing growth process according to the following chemicalreactions:

XH₂S+Cu

CuS_(X)+XH₂; or XS_(n)+nCu

nCuS_(X)

XH₂S+2Cu

Cu₂S_(X)+XH₂; or XS_(n)+2nCu

nCu₂S_(X)

The rate of growth of film 12 can be increased or decreased by raisingor lowering, respectively, the temperature of structure 100 and/or thereactant gas. The growth rate can also be increased or decreased byincreasing or decreasing, respectively, the concentration (or partialpressure) of the reactant gas.

For example and without limitation, copper sulfide film 12, having athickness of about 10 Å to about 2,000 Å, can be grown by an intermixingsulfidation process on the top surface of copper conductor 18 bysubjecting a wafer with exposed conductor 18 to an H₂S gas (or a gasmixture of H₂S with inert gas, such as argon or nitrogen), or to asublimed sulfur vapor, at a temperature from about 25° C. to about 500°C. The dry sulfidation can be performed in a furnace, such as a rapidthermal processing (RTP) furnace, a CVD chamber, or a plasma enhancedCVD (PECVD) chamber at sulfidation times ranging from a few seconds toabout 10 minutes. The higher the substrate temperature and/or the longerthe exposure time, the thicker the copper sulfide film 12, and viceversa.

Copper sulfide film 12 may also be grown by an intermixing growthprocess in accordance with one or more further embodiments of thepresent invention by reacting the exposed top surface of copperinterconnect 18 with a wet solution which contains one or moresulfur-bearing compounds comprising sulfur atoms, molecules, or ions,such as, for example and without limitation, solutions comprisingelemental sulfur (S_(n)) or sulfide ions (S⁻²) of Na₂S, K₂S, (NH₄)₂S,and dissolved H₂S. It is believed that in accordance with suchembodiments, copper sulfide film 12 is grown by an intermixing growthprocess according to the following chemical reactions:

XS⁻²+2XH₂O+Cu

CuS_(X)+2XOH⁻+XH₂;

or XS_(n)+nCu

nCuS_(X)

XS⁻²+2XH₂O+2Cu

Cu₂S_(X)+2XOH⁻+XH₂;

or XS_(n)+2nCu

nCu₂S_(X)

In accordance with one or more of such embodiments, dipping or sprayingthe top surface of copper interconnect 18 in the wet solution iscontinued until a predetermined thickness of film 12 is approached orattained (as will be described below, it is believed that thepredetermined thickness may be a self-limited thickness). The rate ofgrowth of film 12 can be increased or decreased by raising or lowering,respectively, the temperature of the wet solution and/or structure 100.The growth rate of film 12 can also be increased or decreased byincreasing or decreasing, respectively, the concentration of thesulfur-bearing reactant in the solution.

It may be advantageous to grow film 12 by an intermixing self-limitinggrowth process, to its self-limited thickness at a temperature higher(for example and without limitation, by at least 50° C., and morespecifically, by at least 100° C.) than the operational temperaturesattained during device operation. It is believed that this will help toreduce copper diffusion across film 12 during operation of the device,or it might even substantially prevent such copper diffusion. In such acase, passivation film 12 can also function (and be used) as a diffusionbarrier layer, in addition to its passivation role (by immobilizing topsurface atoms of conductor 18). However, as is well-known, the actualgrowth temperature might be limited by a thermal budget, or by otherprocessing and/or integration considerations, and a trade-off might berequired. In light of this information, appropriate values oftemperature can be determined for a particular application by one ofordinary skill in the art routinely and without undue experimentation.“Self-limited thickness” is defined herein as the thickness attainedafter a certain growth time, Δt (at a specific growth temperature),which increases by less than about 25% when the growth time is extendedby another Δt, or more. For example, if the thickness of film 12 isabout 200 Å after 5 minutes growth at a given temperature, and it isless than about 250 Å after additional 5 minutes growth at the sametemperature, then the self-limited thickness of film 12 is about 200 Å.The self-limited thickness is a strong function of the growthtemperature, increasing with the growth temperature. It is believed thatthe thickness of passivation film 12 has to be larger than about 300 Åand, probably larger than about 500 Å, for it to function as anefficient diffusion barrier. Using film 12 alone as a diffusion barrier(see FIG. 1( a)), without dielectric barrier layer 19, would have thedistinct advantages of significantly reducing the effective dielectricconstant (k_(eff)) of the multilevel interconnect, while improving itsreliability, structural strength, and integrity.

In General, the Cu₂S_(X) phases are thermally more stable than theCuS_(X) phases. For example, the Cu₂S_(X) δ-phase has a maximum meltingpoint of 1,131° C., whereas the CuS_(X) ε-phase is not stable above 507°C., and undergoes phase transformations at 76° C. and at 115° C. SeeMetals Handbook, 8^(th) Edition, Vol. 8, pages 297, 300, 358, AmericanSociety for Metals, 1973. A reference herein to a Cu₂S_(X) phase mayalso include the case of more than a single phase and, similarly, areference herein to a single CuS_(X) phase may also include the case ofmore than a single phase. It is believed that when film 12 comprises theCu₂S_(X) phase, it is more stable and, therefore, may be more desirable.As a result, if film 12 is formed (by intermixing growth) by reacting asulfur-bearing reactant gas or vapor on copper conductor 18, attemperatures above about 507° C., only the Cu₂S_(X) phase is formed.Similarly, if film 12 is first formed as the phase CuS_(X) (alone or ina multiple phase structure) and, if the film is subsequently heated (orannealed) to above about 507° C., then film 12 will convert to theCu₂S_(X) phase.

However, depending on the thickness of film 12 and subsequent heating(or annealing), film 12 may convert entirely into the Cu₂S_(X) phase ateven lower temperatures than about 500° C. For example, it is believedthat a relatively thin (about 30 Å to about 200 Å) copper sulfide(s)film 12 will convert entirely into the Cu₂S_(X) phase by annealing itfor a relatively short time (about 0.5 minute to about 10 minutes) at atemperature between about 100° C. to about 400° C. and, morespecifically, between about 150° C. to about 300° C. It is believed thatfilm 12 converts to the Cu₂S_(X) phase by reacting with excess copper onthe conductor 18 side, while there is no fresh supply of sulfur specieson the other side of film 12. Thicker film 12 may require longerannealing time and/or higher annealing temperature to fully convert intothe Cu₂S_(X) phase. Subsequent annealing of film 12 can be performed asa separate dedicated processing step, or during another elevatedtemperature processing step such as, for example and without limitation,during deposition of dielectric barrier 19 in FIG. 1( b), for example,by a CVD or a PECVD process. For example, it is believed that when thethickness of film 12 is in a range of about 30 Å to about 200 Å, theprocessing temperature during a subsequent CVD or plasma enhanced CVD(PECVD) deposition step (for example and without limitation, of asilicon nitride or a silicon carbide barrier layer 19) is sufficientlyhigh and is present for a long enough time to fully convert any otherphase(s) of film 12 into the Cu₂S_(X) phase.

In accordance with one or more still further embodiments of the presentinvention, film 12 grown by an intermixing growth process on copperinterconnect 18 comprises one or more of CuSe_(X), Cu₂Se_(X), CuTe_(X),Cu₂Te_(X) (where 0.7≦X≦1.3; and X=1.0 for stoichiometriccompounds)—where copper selenide refers to CuSe_(X) and/or Cu₂Se_(X) andcopper telluride refers to CuTe_(X) and/or Cu₂Te_(X). In still furtherembodiments, film 12 comprises one or more of CuS_(X), Cu₂S_(X),CuSe_(X), Cu₂Se_(X), CuTe_(X), Cu₂Te_(X) (where 0.7≦X≦1.3; and X=1.0 forstoichiometric compounds), and other materials comprising one or more ofthese compounds.

Copper selenide can be grown by an intermixing growth process byreacting the exposed top surface of copper interconnect 18 with a wetreactant, or a dry reactant gas (or gas mixture) or vapor of one or moreselenium-bearing compounds comprising selenium atoms, molecules, orions. Copper telluride can be grown by an intermixing growth process byreacting the exposed top surface of copper interconnect 18 with a wetreactant, or a dry reactant gas (or gas mixture) or vapor of one or moretellurium-bearing compounds comprising tellurium atoms, molecules, orions. For example, in order to grow copper selenide by an intermixinggrowth process on the copper surface, the copper surface may be reactedwith (for example and without limitation) H₂Se, Na₂Se, K₂Se, or(NH₄)₂Se. Similarly, in order to grow copper telluride by an intermixinggrowth process on the copper surface, the copper surface may be reactedwith (for example and without limitation) H₂Te, Na₂Te, K₂Te, or(NH₄)₂Te.

It is believed that one or more of the above-described embodiments forgrowing film 12 by an intermixing growth process is a self-limitingprocess. In particular, it is believed that the process is self-limitingby copper and/or sulfur (or sellenium or tellurium) diffusion through(or across) the film as it grows. In particular, it is believed that asthe thickness of the growing film increases, the flux of copper speciesthat travel from copper interconnect 18 through film 12 and/or the fluxof sulfur (or sellenium or tellurium) species that travel from thesurface through film 12 slows down until it or they become substantiallynegligible or insignificant. In particular, it is believed that aself-limited thickness of film 12 depends on temperature, the density ofthe film, and its morphology. For example, if the growth temperature ishigher, the limiting thickness will be greater (assuming sufficientgrowth time of the film to its self-limited thickness), and the filmwill form faster. However, it is also believed that, if the density ofthe film is so low that there are high rates of diffusion, or if thefilm contains voids and/or many defects, the process may not beself-limiting. It is further believed that the process is confined to aself-limiting process by enabling diffusion to take place fast enough(during film formation) to growth sites to avoid forming voids. This maybe done by raising the growth temperature to ensure that the diffusingspecies can reach their proper growth sites without forming voids. Inlight of this information, appropriate values of temperature andreactant concentration or amounts can be determined for a particularapplication by one of ordinary skill in the art routinely and withoutundue experimentation.

It should be understood that in some semiconductor processes, the use ofcompounds containing alkali metal ions might be problematic due to thepossibility of contamination. In such cases, for example and withoutlimitation, ammonium sulfide or dissolved H₂S may be used to avoid suchalkali metal contamination. Other chemical reagents which comprisesulfur such as, for example and without limitation, elemental sulfur(S), SO₂, sulfites, thioacetamide, thiourea, or thiosulfates may also beused to form film 12. As such, one or more embodiments of the presentinvention include the use of any chemical reagent suitable for reactionwith the exposed top surface of conductor 18 to form passivation film 12comprising a copper sulfide.

Advantageously, film 12 formed as described above is grown on top ofconductor interconnect 18, and does not grow on top field 14 of thesurrounding dielectric layer 11. As such, growth of passivation film 12by an intermixing growth process provides a selective process whichadvantageously helps avoid current leakage through dielectric layer 14.It is further believed that the passivating reactant can advantageouslypassivate any exposed copper residue (contamination) left on (orembedded onto) field 14 of surrounding dielectric 11 by a previous CMPstep. This is advantageous because it may further reduce leakagecurrents between interconnect lines. In addition, and advantageously inaccordance with one or more embodiments of the present invention relatedto copper interconnect, it is believed that passivation film 12 ischemically bonded to the copper conductor 18 underneath it, therebyadhering well to the top surface of copper (or copper alloy) conductorinterconnect 18. As such, it is believed that film 12 can reduce oreliminate copper interfacial surface diffusion and, thereby, reduce oreliminate electromigration (EM).

Copper sulfide passivation film 12 described above is furtheradvantageous because it also adheres well to dielectric layers such as,for example and without limitation, dielectric layers that overlay instructures used to fabricate devices such as semiconductor devices,thereby improving the mechanical strength and the structural integrityof multi-level metallization devices. Furthermore, since copper sulfidefilm 12 is not a dielectric material (actually it is conductive, havinga resistivity ρ value in a range of about 10⁻⁴ to about 10⁻² ohm-cm), itdoes not increase the effective dielectric constant (k_(eff)) ofstructures 100 or 110. In accordance with one or more embodiments, thethickness of passivation film (or layer) 12 may be in a range from about10 Å to about 500 Å and, more specifically, in a range from about 50 Åto about 200 Å.

B. Deposition

In accordance with one or more embodiments of the present invention,film 12 may be deposited upon the exposed top surface of conductorinterconnect 18. Such a deposition may be carried out by a: (a) drydeposition process such as, for example and without limitation, atomiclayer deposition (ALD) or chemical vapor deposition (CVD); (b) physicalvapor deposition (PVD) process such as, for example and withoutlimitation, sputtering or evaporation; or (c) wet deposition processsuch as, for example and without limitation, chemical bath deposition,electrodeposition, or electroless deposition. Except for electrolessdeposition and electrodeposition, the other deposition processesmentioned above are not selective. For example, using such otherdeposition processes, copper sulfide will be deposited over the topsurface of copper interconnect 18 and the top surface of surroundingdielectric 11 on field 14. As such, the use of non-selective depositionprocesses may require additional steps for removing copper sulfidedeposited over the top surface of dielectric 11 in field 14. Inaccordance with one or more such embodiments, it is believed that strongadhesion is provided because at least one of such materials ischemically bonded to material at the exposed top surface conductorinterconnect 18. In addition, and advantageously in accordance with oneor more embodiments of the present invention, because film 12 ischemically bonded to copper underneath it, film 12 adheres well to thetop surface of copper interconnect 18. As such, it is believed that film12 can reduce or eliminate copper surface diffusion, and thereby reduceor eliminate electromigration (EM). It is believed that chemical bondingis enhanced if the temperature of the substrate is elevated duringdeposition and/or during successive processing steps entailed infabricating a device.

In accordance with one or more embodiments of the present invention, itis believed that copper atoms at the surface of copper interconnect 18are chemically bound, for example and without limitation, in achalcogenide compound comprised of one or more constituents that have ahigh affinity for copper. In accordance with one or more suchembodiments, film 12 may be utilized to passivate the top surface ofconductor interconnect 18. In accordance with one or more suchembodiments, the thickness of passivation film layer 12 may be in arange from about 10 Å to about 500 Å, and more specifically in a rangefrom about 50 Å to about 200 Å. In addition, film 12 may reduce theeffective dielectric constant k_(eff) of a multi-level interconnectstructure by reducing the required thickness of (or entirelyeliminating) the relatively high-k silicon nitride (or other high-k)dielectric capping layer. Although the description above referred mostlyto copper metal (Cu) interconnect and copper sulfide (CuS_(X) and/orCu₂S_(X), where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds)films, it should be understood by those skilled in the art that one ormore embodiments of the present invention also may be utilized withinterconnects comprising any highly conductive metal or alloy, such as,for example and without limitation, silver metal (Ag) or alloys whichcomprise one or more of the metals Cu and Ag. Similarly, it should beunderstood that one or more embodiments of the present invention alsoinclude films which comprise silver sulfide (AgS_(X) and/or Ag₂S_(X),where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds) and/or mixturesof other sulfide compounds comprising one or more atoms selected fromthe group consisting of Cu and Ag. In addition, it should be understoodthat one or more embodiments of the present invention also include filmswhich comprise copper selenides and/or tellurides, silver selenidesand/or tellurides, and mixtures thereof (consisting of one or more ofcopper and/or silver sulfides, selenides, and tellurides).

Copper sulfide passivation film 12 described above with respect tointermixing growth and deposition processes is further advantageousbecause it also adheres well to dielectric layers such as, for exampleand without limitation, dielectric layers that overlay in structuresused to fabricate devices such as semiconductor devices, therebyimproving the mechanical strength and the structural integrity ofmulti-level metallization devices. Furthermore, since copper sulfidefilm 12 is not a dielectric material (actually it is conductive, havinga resistivity ρ value in a range of about 10⁻⁴ to about 10⁻² ohm-cm), itdoes not increase the effective dielectric constant (k_(eff)) ofstructures 100 or 110. In accordance with one or more embodiments, thethickness of passivation film (or layer) 12 may be in a range from about10 Å to about 500 Å and, more specifically, in a range from about 50 Åto about 200 Å.

C. Capping Passivation Plus Capping Dielectric Barrier

FIG. 1( b) shows a pictorial representation of a transverse (along thewidth) cross-section (not to scale for ease of understanding) ofstructure 110 used to fabricate, for example and without limitation, asemiconductor device that includes structure 100 shown in FIG. 1( a) anda dielectric layer 19 that overlays structure 100. In accordance withone or more embodiments of the present invention, dielectric barrierlayer 19 may be utilized as an etch-stop layer (ESL) during etching ofsuccessive vias and/or trenches for a higher metallization level.Dielectric barrier layer 19 may also serve as an additional cappingdiffusion barrier against copper outdiffusion. Dielectric barrier layer19 may comprise, for example and without limitation, silicon nitride,silicon carbide, silicon carbide nitride, silicon carbide nitride oxide,silicon nitride oxide, SiC_(X)H_(Y), or SiC_(X)O_(Y)H_(Z). Dielectricbarrier layer 19 may be deposited using any one of a number ofdeposition processes that are well known to those skilled in the art,for example and without limitation, by a chemical vapor deposition (CVD)or by a plasma enhanced CVD (PECVD), at a temperature range of about400-500° C., or less. As described above, passivation film 12 adhereswell to dielectric layers, and as such, film 12 adheres well todielectric layer 19. As such, passivation film 12 may significantlyimprove the strength and structural integrity of multi-levelmetallization devices.

It is believed that conventional interfaces between copper lines and thecapping dielectric barrier (such as silicon nitride or silicon carbide)effectively generate micro-crack precursors which, under thermal and/ormechanical stress, may propagate into the surrounding (mechanicallyweak) dielectric, thus adversely affecting the structural integrity. Itis further believed that, many of the current mechanical strength andstructural integration problems associated with low-k dielectrics inadvanced interconnect structures (such as CMP delamination and packagingproblems), are related to such interfacial micro-cracks precursors.Thus, interposing a copper chalcogenide film, such as a copper sulfidefilm 12, between the copper lines 18 and the capping dielectric barrierlayer 19, with strong adhesion to both, can effectively mitigate oreliminate the deleterious interfacial micro-crack precursors, therebyimproving the mechanical strength and structural integrity of thedevice.

D. Further Processing

When higher levels interconnects are used (not shown), successive vias(not shown) connecting conductor 18 to an upper level metallizationinterconnect are formed. In order to minimize the successive viasresistance, it may be desirable and/or advantageous to removepassivation film 12 from under the bottom of the successive vias (notshown), prior to copper or silver filling, by a short etching step. Inaccordance with one or more embodiments of the present invention,passivation film 12 can be selectively removed from under the bottom ofsuccessive vias by an etching step such as, for example and withoutlimitation, using a directional dry etching technique such as sputteretching, ion milling, or reactive ion etching (RIE) through thesuccessive vias. Film 12 may also be selectively removed from under thebottom of the vias by wet chemical etching through the successive vias,utilizing, for example and without limitation, HNO₃ and/or H₂SO₄. Wheredielectric barrier layer 19 is formed over film 12, the etching of film12 can be integrated into the removal (etching) step of layer 19 fromthe successive vias' bottom, usually by a RIE technique. The chemistryused for etching the dielectric barrier layer 19 may also be utilizedfor the RIE etching of film 12. Alternatively, film 12 may be removed bya separate subsequent step, utilizing ion milling, or by a different RIEgas chemistry, suitable for the removal of film 12.

Structures comprising successive vias disposed over film 12 and/ordielectric barrier 19, with film 12 and/or dielectric barrier 19selectively removed from the successive vias' bottom, ensure minimalvias resistance by direct metallic contact to the preceding (i.e.,lower) copper metallization level 18.

Sidewalls and Bottom Encasing

FIG. 2( a) shows a pictorial representation of a transverse (along thewidth) cross-section (not to scale for ease of understanding) ofstructure 200 used to fabricate, for example and without limitation, ametallic interconnect in a semiconductor device, wherein opening 13 hassidewalls surfaces 15 and bottom surface 17 covered with metallicbarrier layer 16. Metallic barrier layer 16 is covered in turn, withfilm 22 in accordance with one or more embodiments of the presentinvention. Opening 13 of structure 200 may subsequently be filled, forexample and without limitation, using electroplating (or electrofilling)methods. Structure 200 may be fabricated as follows. In accordance withany one of a number of methods that are well known to those of ordinaryskill in the art, dielectric layer 11 may be deposited over substrate10, which substrate 10 may comprise one or more layers such as, forexample and without limitation, a lower metallization level and/oranother dielectric layer. Next, in accordance with any one of a numberof methods that are well known to those of ordinary skill in the art,opening 13 having sidewalls surfaces 15 and bottom surface 17 may bepattern-etched in dielectric layer 11, and barrier layer 16 may bedeposited over sidewalls 15 and bottom surface 17 of opening 13.Metallic barrier layer 16 may comprise, for example and withoutlimitation, at least one layer of one or more refractory metals oralloys comprising refractory metals, such as Ta, TaN_(X), binaryTa/TaN_(X), Ru, TaSi_(X)N_(Y), WN_(X), binary Ti/TiN_(X), TiSi_(X)N_(Y),or WSi_(X)N_(Y). Next, film 22 is grown by an intermixing growth processor by a deposition process over metallic barrier layer 16 in accordancewith one or more embodiments of the present invention. Next, one or moreseed layers 24 are deposited over film 22 in accordance with any one ofa number of methods that are well known to those of ordinary skill inthe art. Although FIGS. 2( a) and 2(b) show a single seed layer 24, itis within the scope of the invention that layer 24 may also comprise twoor more layers, deposited in two or more steps, such as, for example andwithout limitation, where one step produces a relatively thick seedlayer which may be non-conformal (or discontinuous), and another stepproduces a relatively thin conformal (i.e., continuous on the bottom 17and sidewalls 15) seed layer.

In accordance with one or more embodiments of the present invention, arelatively thin conductive continuous (or conformal) Ru layer (such asdeposited by PVD, ALD, or CVD techniques) serves as a barrier layerand/or as a seed layer, followed by a thicker PVD seed layer 24(comprising Cu, Ag, or an alloy comprising one or more of these metals).The Ru layer can be used as a single barrier layer 16 or, preferably, ina combination (not shown) with one or more other metallic barrier layers(such as Ta, TaN_(X) or bilayer Ta/TaN_(X)). While the conformalconductive Ru seed layer ensures continuous sidewalls and bottomcoverage, the thicker PVD seed layer provides sufficient field surfaceconduction, required for void-free electrofilling and for adequateplating uniformity across a wafer. The interposed Ru layer provides goodadhesion to both the refractory metal barrier 16 on one side and to Cuon the other side, thus serving as a “glue”, enhancing strong adhesionbetween the two. When Ru layer is used as a single barrier layer 16, italso provides good adhesion to dielectric 11. In such embodiments, theRu layer can be used in combinations with, or without, film 22.

As defined herein, “conformal” means “continuous”, and “substantiallyconformal” means “substantially continuous” coverage of a layer on atleast the sidewalls (preferably also on the bottom) of the openings.

In accordance with one or more preferred embodiments of the presentinvention, layer or film 22 comprises one or more of CuS_(X), Cu₂S_(X),CuSe_(X), Cu₂Se_(X), CuTe_(X), Cu₂Te_(X) (where 0.7≦X≦1.3; and X=1.0 forstoichiometric compounds), and other materials comprising one or more ofthese compounds. In accordance with one or more further embodiments ofthe present invention, film 22 may also comprise silver sulfide (AgS_(X)and/or Ag₂S_(X), where 0.7≦X≦1.3; and X=1.0 for stoichiometriccompounds) and/or other mixtures of sulfides comprising one or moreatoms selected from the group consisting of Cu and Ag. Advantageously inaccordance with one or more embodiments of the present invention, it isbelieved that because film 22 is chemically bonded to barrier 16 and tocopper (or silver) seed layer 24, film 22 adheres well to both. Inaccordance with one or more further embodiments of the presentinvention, a conductive conformal film 22 serves as a first seed layer,followed by a thicker PVD seed layer 24 (comprising Cu, Ag, or an alloycomprising one or more of these metals). While the first seed layer 22ensures continuous sidewalls and bottom coverage, the thicker PVD seedlayer provides sufficient field surface conduction, required forvoid-free electrofilling and for adequate plating uniformity across awafer. As such, after electrofilling to form a copper (or silver)interconnect in opening 13, film 22 may advantageously also function asa passivation layer on sidewalls and/or on the bottom surfaces of theinterconnect to reduce or eliminate EM and/or SIV, and to enhanceadhesion between the copper (or silver) interconnect and metallicbarrier 16. Film 22 may also function as a diffusion barrier to reduceor eliminate copper (or silver) outdiffusion into surrounding dielectric11.

FIG. 2( b) shows a pictorial representation of a transverse (along thewidth) cross-section (not to scale for ease of understanding) ofstructure 210 used to fabricate, for example and without limitation, asemiconductor device that is the same as structure 200 shown in FIG. 2(a), except that barrier layer 16 is not used. In accordance with one ormore such embodiments of the present invention, film 22 functions as apassivation film and/or as a diffusion barrier to prevent or reducecopper or silver outdiffusion, depending on the application, intodielectric 11 from an interconnect that is subsequently formed inopening 13.

In accordance with one or more embodiments of the present invention,film 22 in FIGS. 2( a) and 2(b) is substantially conformal (i.e.,continuous) and may be utilized to passivate the sidewalls and bottomsurfaces of an interconnect conductor that fills opening 13. Inaccordance with one or more such embodiments, the thickness of filmlayer 22 may be in a range from about 10 Å to about 500 Å and, morespecifically in a range from about 20 Å to about 200 Å.

In accordance with one or more embodiments of the present invention, itis believed that copper atoms at interfaces with film 22, such as seedlayer 24 and/or copper-filled conductor interconnect 18 (in FIG. 1), arechemically bound, for example and without limitation, in a chalcogenidecompound comprised of one or more constituents that have a high affinityfor copper.

A. Deposition

In accordance with one or more embodiments of the present invention,film 22 may be deposited using a: (a) dry deposition process such as,for example and without limitation, atomic layer deposition (ALD) orchemical vapor deposition (CVD); (b) physical vapor deposition (PVD)process such as, for example and without limitation, sputtering orevaporation; or (c) wet deposition process such as, for example andwithout limitation, chemical bath deposition, electrodeposition, orelectroless deposition. In accordance with a preferred embodiment, film22 is deposited by a conformal deposition process, such as ALD(preferably), CVD, electroless, or electrodeposition. For example andwithout limitation, in accordance with one or more embodiments, an ALDtechnique or a CVD technique may be used to deposit a conformal CuS_(X)or Cu₂S_(X) film 22 inside opening 13 of high aspect ratio (HAR). Suchembodiments provide a continuous film 22 over sidewalls 15, which mayeven comprise negative slopes, nooks, crevices, or crannies For anexample of an ALD of CuS_(X), see a publication entitled “Growth ofconductive copper sulfide thin films by atomic layer deposition” byJohansson et al., in J. Mater. Chem., Vol. 12, pp. 1022-1026 (2002). Forexample and without limitation, organometallic precursors such asCu(thd)₂, Cu(hfac)₂, or (hfac)Cu(tmvs) can be reacted with H₂ 5 gas inALD or CVD processes to deposit conformal CuS_(X) or Cu₂S_(X) films. Dueto the high affinity of refractory metals to carbon and oxygen, ametallic barrier layer 16, which is based on a refractory metal oralloy, tends to form interfacial oxides and/or carbides by reacting withthe organic part of the copper organometallic precursors. Suchinterfacial oxides and/or carbides may impair adhesion (and/ornucleation) of copper sulfide film 22 to metallic barrier 16. For thisreason, other copper precursors comprising inorganic compounds which donot include carbon and/or oxygen atoms can be used. For example andwithout limitation, precursors comprising copper halides, such as copperchlorides, copper bromides, or copper iodides may be used instead of thecopper organometallic precursors.

In accordance with one or more such embodiments, it is believed thatadvantageously strong adhesion is provided because at least one of suchmaterials comprising film 22 (copper or silver chalcogenide) ischemically bonded to material at the underlying surfaces of barrier 16and to overlying seed layer(s) 24. It is further believed that film 22is chemically bonded to metallic barrier 16 underneath it by sharingchalcogenide atoms (S, Se, or Te) with it, and to seed layer(s) 24 aboveit by sharing chalcogenide atoms with film 24, thus providing excellentadhesion to both. As such, it is believed that film 22 can reduce oreliminate copper interfacial surface diffusion, and thereby reduce oreliminate electromigration (EM) and/or stress induced voids (SIV), whileimproving structural strength and integrity. It is also believed thatchemical bonding is enhanced if the temperature of the substrate iselevated during deposition and/or during successive processing stepsentailed in fabricating a device. When no barrier layer 16 is used, suchas structure 210 of FIG. 2( b), it is similarly believed that adhesionof film 22 to dielectric 11 is promoted by sharing or substitutingchalcogenide atoms or ions of S, Se, or Te with dielectric 11.

Film 22 can be grown on barrier layer 16 (FIG. 2( a)), or directly ondielectric 11 (FIG. 2( b)), by dry or by wet deposition techniques. Thedry deposition techniques may include ALD, CVD, or PVD. Note that theALD method may be particularly advantageous due to its highly conformalnature. As such, it can coat all surfaces continuously, including hardto reach negative slopes, crevices, nooks and crannies For an example ofa method for ALD deposition of copper sulfide, see an article byJohansson et al. entitled “Growth of conductive copper sulfide thinfilms by atomic layer deposition” in Journal of Materials Chemistry,2002, vol. 12, pp. 1022-1026, incorporated herein by reference. The wetdeposition techniques may include, for example and without limitation,electroless, electroplating, or chemical bath deposition techniques.

In one or more other embodiments, sulfur (atoms, molecules, or ions) arefirst deposited directly onto, and/or “impregnated” into, the surface ofdielectric 11, and then reacted with a copper-bearing reactant (such asaqueous solution of cuprous or cupric ions) to form film 22 byintermixing growth. Such embodiments might be particularly useful whenusing porous low-k dielectric 11, capable of absorbing appreciableamounts of the sulfur species.

B. Intermixing Growth

In accordance with one or more embodiments of the present invention,layer 22 can be grown by an intermixing growth process by firstdepositing a thin layer of copper or silver (such as by ALD, CVD,electrodeposition, or electroless techniques) over barrier layer 16,followed by an intermixing growth process like those described above forgrowing film 12 of FIG. 1. Accordingly, film 22 is grown in two steps:(a) a copper (or silver) layer (not shown) is first deposited (by a dryor by a wet deposition technique on metallic barrier 16 or directly ondielectric 11 (see FIG. 2( b)) and, (b) reacting the copper (or silver)layer with a sulfur (or sellenium or tellurium) bearing reactant to formfilm 22 by intermixing growth. For example, a copper layer can bedeposited on barrier 16 or directly on dielectric 11 by an ALD, CVD,PVD, or electroless technique, followed by reacting the copper (orsilver) layer with a (wet or dry) sulfur-bearing reactant, such as H₂Sor elemental sulfur.

In yet another embodiment (not shown), one or more copper seed layer(s)24 is first deposited over metallic barrier layer 16 (see FIG. 2( a)),and the copper seed layer (s) 24 is then reacted with a dry or wetchalcogenide-bearing reactant to form film 22. Partially consumed seedlayer(s) 24 thus underlay film 22 (not shown), and electrofilling ofopening 13 is performed directly onto film 22.

Advantageously, film 22 may provide improved device integrity andreliabilty because it may act to reduce voids in subsequentlyelectroplated conductor that fills opening 13, when seed layer 24 is toothin and/or when seed layer(s) 24 is discontinuous on sidewalls 15.

Further Processing

1. In order to minimize via resistance, it may be desirable oradvantageous to remove film 22 from bottom 17 of opening 13 (such as viain FIGS. 2( a) and 2(b)) prior to copper or silver filling. Inaccordance with one or more embodiments of the present invention, film22 can be removed from bottom 17 of vias 13 by an etching step such as,for example and without limitation, using a directional dry etchingtechnique such as sputter etching, ion milling, or reactive ion etching(RIE). Film 22 may also be removed from bottom 17 of via 13 by wetchemical etching such as, for example and without limitation, using HNO₃and/or H₂SO₄. Structures comprising vias with layer 22 removed frombottom 17 are shown, for example and without limitation, in FIG. 4. Suchremoval (as well as the removal of barrier layer 16 from the via'sbottom) ensures minimal via resistance, by providing copper to coppercontact with a preceding (i.e., lower) metallization level (see 10 inFIG. 4). Removal of metallic barrier 16 from the via's bottom furtherimproves device reliability by mitigating or eliminating EM and/or SIVproblems related to the vias' bottom.

As was discussed above in conjunction with FIGS. 2( a) and 2(b), seedlayer(s) 24 is deposited over film 22 inside opening 13 and over field14. In accordance with one or more embodiments of the present invention,a continuous film 22 on the sidewalls 15 facilitates the use of arelatively thick seed layer 24 (which may be discontinuous inside theopening), which can be deposited, for example, by a PVD technique suchas sputtering, ion plating, or evaporation. The main purpose ofdepositing the relatively thick seed layer 24 is to provide sufficientseed layer thickness for adequate surface conduction over field 14.Adequate surface conduction is required to minimize “terminal effect”(i.e., a thickness non-uniformity across a wafer due to IR-drop from thewafer's edge contact to its center). Adequate surface conduction isrequired for good uniformity of an electroplated conductor across awafer and for void-free electrofilling. The thickness of seed layer 24can be in a range from about 200 Å to about 2,000 Å over field 14, andmore particularly in a range from about 300 Å to about 1,000 Å overfield 14. As is discussed below, in accordance with one or moreembodiments of the present invention, seed layer 24 (which may bediscontinuous inside the opening) may also be used as a (sacrificial)mask during removal of film 22 and/or metallic barrier layer 16 from avia's bottom 17.

2. In still another embodiment, as shown in FIG. 2( b), film 22 may beformed directly (without barrier layer 16) over dielectric 11 and oversubstrate 10 at bottom 17 of opening 13 and, following its formation, anon-conformal seed layer 24 is deposited over film 22. Then, if desired,film 22 may be removed from bottom 17 by an etching step, usingnon-conformal seed layer 24 as a mask to protect layer 22 over field 14and sidewalls 15. The etching can be performed by wet chemical etching(for example, with HNO₃ and/or H₂SO₄) or, more preferably, bydirectional (anisotropic) dry etching such as by sputter etching, ionmilling, or reactive ion etching (RIE). Then, in order to improveconduction of sidewalls 15, a relatively thin conformal seed layer (notshown) may be deposited over the entire structure. The conformal seedlayer may be deposited following the step of removing film 22 frombottom 17. The conformal seed layer may preferably be deposited by anALD or a CVD technique. However, it may also be deposited by any otherconformal deposition technique, such as electroless orelectrodeposition. In an alternative embodiment, a relatively thinconformal seed layer can be deposited as part of a combined seed layers24 directly over film 22, followed by the deposition of a thicker seedlayer (which can be non-conformal), to form a combined seed layer 24.This embodiment is particularly advantageous in embodiments where thereis no removal of film 22 from the bottom 17.

3. In accordance with one or more further embodiments, film 22 may alsoserve as a conformal seed layer. In accordance with further suchembodiments, another seed layer, which may be non-conformal, can bedeposited thereon.

Further Structures

1. FIG. 3( a) shows a pictorial representation of a transverse (alongthe width) cross-section (not to scale for ease of understanding) ofstructure 300 used to fabricate, for example and without limitation, aconductor line in a metallic interconnect in a semiconductor device.Structure 300 comprises an embedded or filled conductive interconnect 18in dielectric 11, with its sidewalls 15 encased with film 30, and itstop surface covered with capping film 32, in accordance with one or moreembodiments of the present invention. Capping film 32 may be fabricatedusing any of the above-described methods relating to film 12 of FIGS. 1(a) and 1(b). FIG. 3( a) also shows metallic barrier layer 16 formed oversidewalls 15 and bottom 17 of the interconnect line embedded indielectric 11. FIG. 3( a) also shows a film or layer 30 disposed betweenmetallic barrier layer 16 and metallic conductor 18. Film 30 may befabricated using any of the above-described methods relating to film 22of FIGS. 2( a) and 2(b). In accordance with one or more embodiments ofthe invention, film (or layer) 30 passivates the sides of conductor 18(which conductor may comprise Cu, Ag, or an alloy comprising one or moreof these metals), and capping film (or layer) 32 passivates the topsurface of conductor 18. Structure 300 shown in FIG. 3( a) may befabricated by starting with structure 200 shown in FIG. 2( a),electrofilling opening 13 with conductor 18, and removing by aplanarization technique, such as, for example, a CMP technique, theexcess plated conductor 18 over opening 13 (not shown), and the metallicbarrier 16 and film 22 from the field 14 of dielectric 11. What was film22 in FIG. 2( a), will thus end up as film (or layer) 30 in FIG. 3( a).As for film 22 described above, layer 30 advantageously comprises one ormore chalcogenide materials selected from the group consisting of coppersulfide, copper selenide, copper telluride, silver sulfide, silverselenide, silver telluride, and mixtures of two or more of thesechalcogenides.

Advantageously, in accordance with one or more embodiments of thepresent invention, it is believed that because film 30 is chemicallybonded to metallic barrier layer 16 and to copper (or silver) conductor18, film 30 adheres well to both. As such, film 30 may advantageouslyfunction as a passivation layer on sidewalls 15 and bottom 17 and/or asa barrier layer against copper (or silver) outdiffusion into surroundingdielectric 11, thereby reducing or eliminating EM and/or SIV. Similarly,it is believed that because film 32 is chemically bonded (and adhereswell) to conductor 18, film 32 may function as a passivation cappingand/or barrier capping layer over conductor 18.

FIG. 3( b) shows a structure 310, similar to structure 300 of FIG. 3(a), but without metallic barrier layer 16. In accordance with one ormore embodiments of the present invention, film 30 functions as apassivation layer and/or as a barrier layer against outdiffusion ofconductor 18 into dielectric 11.

2. FIG. 4( a) shows a pictorial representation of a longitudinal (alongthe length) cross-section (not to scale for ease of understanding) ofstructure 400 used to fabricate, for example and without limitation, aDual Damascene metallic interconnect in a semiconductor device.Structure 400 comprises an embedded or filled conductive interconnect 18in dielectrics 11 and 40. Conductive interconnect 18 is encased by film42 at sidewalls 15 and (line) bottom 41, and its top surface is coveredwith film 44, in accordance with one or more embodiments of the presentinvention. Structure 400 also comprises a metallic barrier layer 16formed over sidewalls 15 of dielectrics 11, 40 and over line bottom 41.In accordance with one or more embodiments of the invention, film (orlayer) 42 passivates the sides of conductor 18 (which conductor maycomprise Cu, Ag, or an alloy comprising one or more of these metals),and capping film (or layer) 44 passivates the top surface of conductor18. In accordance with one or more embodiments of the invention, film 42and/or barrier 16 are removed from bottom 17 of the via, as shown inFIG. 4( a).

In accordance with one or more embodiments of the present invention,layers or films 42, 44 comprise one or more of CuS_(X), Cu₂S_(X),CuSe_(X), Cu₂S_(X), CuTe_(X), Cu₂Te_(X) (where 0.7≦X≦1.3; and X=1.0 forstoichiometric compounds), and other materials comprising one or more ofthese compounds. In accordance with one or more further embodiments ofthe present invention, films 42, 44 may comprise silver sulfide (AgS_(X)and/or Ag₂S_(X), where 0.7≦X≦1.3; and X=1.0 for stoichiometriccompounds) and/or other mixtures of sulfides comprising one or moreatoms selected from the group consisting of Cu and Ag. Advantageously inaccordance with one or more embodiments of the present invention, it isbelieved that because film 42 is chemically bonded to metallic barrierlayer 16 and to copper (or silver) conductor 18, film 42 adheres well toboth. As such, film 42 may advantageously function as a passivationlayer on sidewalls 15 and/or a barrier layer against copper (or silver)outdiffusion into surrounding dielectrics 11, 40, thereby reducing oreliminating EM and/or SIV. Similarly, it is believed that because film44 is chemically bonded (and adheres well) to the top of conductor 18,film 44 may function as a passivation capping and/or barrier cappinglayer over conductor 18. Film 42 can be deposited or grown by adeposition process or by an intermixing process, similar to depositionor growth of film 22 (in FIGS. 2( a) and 2(b)), in accordance with oneor more embodiments described above. Film 44 can be grown by anintermixing process or deposited similar to growth or deposition of film12 (in FIGS. 1( a) and 1(b)), in accordance with one or more embodimentsdescribed above.

FIG. 4( b) shows a structure 410, similar to structure 400 of FIG. 4(a), but without metallic barrier layer 16. In accordance with one ormore embodiments of the present invention, film 42 functions as apassivation layer and/or as a barrier layer against outdiffusion ofconductor 18 into dielectrics 11 and 40.

Although the description of the embodiments and examples above hasconcentrated on metallic interconnect structures used to fabricate adevice such as a semiconductor integrated circuits, these embodimentscan also be used in the fabrication of other devices, such as (coils in)thin film heads, Micromachined Microelectromechanical Systems (MEMS)devices, or interconnects in high density integrated circuit packages.

Those skilled in the art will recognize that the foregoing descriptionhas been presented for the sake of illustration and description only. Assuch, it is not intended to be exhaustive or to limit the invention tothe precise form disclosed.

1. A method for passivating metallic interconnects, said methodcomprising: forming a metallic conductor embedded in at least onesurrounding dielectric layer, said metallic conductor comprising a metalor alloy chosen from a group consisting of Cu, Ag, and alloys comprisingone or more of these metals, said metallic conductor and said at leastone surrounding dielectric layer having top surfaces; and forming acapping passivation film directly on the top surface of the metallicconductor, but not over the top surface of the at least one surroundingdielectric layer, wherein said capping passivation film comprising oneor more materials selected from the group consisting of copper sulfide,silver sulfide, copper selenide, silver selenide, copper telluride, andsilver telluride, wherein the copper sulfide refers to CuS_(X) orCu₂S_(X), the silver sulfide refers to AgS_(X) or Ag₂S_(X), the copperselenide refers to CuSe_(X) or Cu₂Se_(X), and the copper telluriderefers to CuTe_(X) or Cu₂Te_(X), and wherein 0.7≦X≦1.3.
 2. The method ofclaim 1 further comprising depositing a capping dielectric barrier layerover the capping passivation film.
 3. The method of claim 2 wherein thecapping passivation film has a thickness in a range from about 10 Å toabout 100 Å.
 4. The method of claim 2 wherein the capping passivationfilm has a thickness in a range from about 30 Å to about 200 Å.
 5. Themethod of claim 2 wherein the capping passivation film has a thicknessin a range from about 10 Å to about 50 Å.
 6. The method of claim 2wherein the capping dielectric diffusion barrier layer comprises one ormore materials selected from a group consisting of silicon nitride,silicon carbide, silicon carbide nitride, silicon carbide nitride oxide,silicon nitride oxide, SiC_(X)H_(Y), and SiC_(X)O_(Y)H_(Z).
 7. Themethod of claim 2 wherein the capping passivation film is formed in aplasma enhanced chemical vapor deposition (PECVD) chamber.
 8. The methodof claim 7 wherein the PECVD chamber is the same chamber used fordepositing the capping dielectric barrier layer.
 9. The method of claim2 wherein the capping passivation film comprises copper sulfide.
 10. Themethod of claim 9 wherein the capping passivation film has a thicknessin a range from about 10 Å to about 100 Å.
 11. The method of claim 9wherein the capping passivation film has a thickness in a range fromabout 30 Å to about 200 Å.
 12. The method of claim 9 wherein the cappingpassivation film has a thickness in a range from about 10 Å to about 50Å.
 13. The method of claim 9 wherein the capping dielectric diffusionbarrier layer comprises one or more materials selected from a groupconsisting of silicon nitride, silicon carbide, silicon carbide nitride,silicon carbide nitride oxide, silicon nitride oxide, SiC_(X)H_(Y), andSiC_(X)O_(Y)H_(Z).
 14. The method of claim 9 wherein the cappingpassivation film is formed in a plasma enhanced chemical vapordeposition (PECVD) chamber.
 15. The method of claim 14 wherein the PECVDchamber is the same chamber used for depositing the capping dielectricbarrier layer.
 16. The method of claim 14 wherein a sulfur-bearingreactant is utilized for sulfidation of the top surface of the metallicconductor.
 17. The method of claim 16 wherein the sulfur-bearingreactant is selected from a group consisting of H₂S gas, H₂S gasmixture, and sublimed sulfur vapor.
 18. The method of claim 9 whereinthe capping passivation film is formed by reacting the top surface ofthe metallic conductor with a wet solution containing one or moresulfur-bearing compounds.
 19. The method of claim 18 wherein the wetsolution comprises one or more of dissolved elemental sulfur (S_(n)),sulfide ions (S⁻²), and dissolved H₂S.
 20. The method of claim 2 whereinthe capping passivation film is formed by reacting the top surface ofthe metallic conductor with a wet solution containing one or moresulfur-bearing compounds.
 21. A semiconductor device comprising ametallic interconnect passivated by the method of claim
 2. 22. Asemiconductor device comprising a metallic interconnect passivated bythe method of claim 14.